We build the Unified Engine, an AI accelerator for edge devices, and the Apex GPU, which adds graphics to the same engine. Our 12 nm SoC, now in tape-out, is projected at 20× NVIDIA Jetson performance, under 10 W, at one-fifth the cost.
An AI accelerator for LLMs, VLMs and VLA models at the edge. The FPGA prototype is ready for licensing and deployment, and decodes Gemma 3 1B 2.06× faster than the NVIDIA Jetson Orin Nano at 4.5 W.
The Unified Engine with graphics, targeting Vulkan 1.4 and DirectX 12 Ultimate.
Kintex-7
FPGA prototype
Alveo U50
FPGA accelerator card prototype
Normalized to Jetson Orin Nano. Axelera and Apex FPGA measured on Llama 3.2 1B. SiMa.ai Modalix and Apex FPGA measured on Gemma 4 E2B. Jetson and Apex FPGA measured on Gemma 3 1B. The 12 nm simulation assumes 100 GB/s LPDDR5 bandwidth and 2 Apex Compute engines running in parallel. The 2-engine, 6 GB/s DDR bandwidth scenario is reproducible on FPGA with our GitHub releases.
M=K=N=1024, 42 GFLOPS BF16 peak. Reproduce with our GitHub releases
| Operation | GFLOPS | Of peak |
|---|---|---|
| BF16 matrix multiplication, A·Bᵀ | 40.17 | 95.6% |
| Matmul + bias + activation (GELU / SiLU) | 40.03 | 95.3% |
| Quantized matrix multiplication, BF16 × INT4/FP4 | 40.03 | 95.3% |
| Softmax fused into matrix multiplication | 37.76 | 89.9% |
| Memory-efficient attention kernel | — | ~90% |
| Streaming quantized matvec, decode mode | 31.33 | 74.6% |
Causal attention with bias enabled. Performance by sequence length, in GFLOPS. Peak: 36.87 GFLOPS, 87.8% of theoretical, at sequence length 3072 and head_dim 256.
A 256×2048 @ 2048×1024 matmul split 192/64 across two engines, recorded by the 8,192-timestamp trace buffer. Engine 1 finishes its smaller partition first and halts on the hardware synchronization flag until Engine 0 completes.
Engine 0 192×2048 @ 2048×1024
Engine 1 64×2048 @ 2048×1024
One compiled prefill program handles any prompt up to 192 tokens, and the instruction binary is 10× smaller.
INT4 or NVFP4 is selected for each 64-element K-block by minimizing MSE. Norms and embeddings stay BF16.
One command reflashes, warm-boots the fabric and re-scans PCIe. No power cycle, no host reboot.
Vision and navigation on-board, within a power budget that keeps the aircraft aloft.
Perception, fusion and planning with bounded latency, on the vehicle.
Vision-language and VLA models on-device. The whole policy stays on the robot.
For deployments where data cannot leave the building.
Memory-bandwidth-bound on weight matmul, compute-bound on SRAM operations, with no structural bottleneck in between. LPDDR5 gives about 10× the bandwidth of our current system.
Unified Engine FPGA board
An FPGA PCIe card with two Unified Engines, the XDMA driver, the Python runtime and a working Gemma 3 1B example. The package includes hardware design updates.
Send us the model and the power envelope.
Soma Capital
Argmax